Principal Design Verification Engineer
MM241125
Posted: 11/04/2025
- $150,000-$250,000
- Mountain View, CA
- Permanent
How has GenerativeAI changed the way data center infrastructure is built and scaled? How can a new interconnect architecture reduce bottlenecks in hyper-distributed systems? If you're passionate about building ground-breaking products to connect and move data across AI infrastructure, this opportunity might be for you!
Acceler8 Talent is seeking an experienced Principal Design Verification Engineer to join a mature startup in the Bay Area. As a member of this highly accomplished team, you would collaborate with world-class distributed systems hardware and software architects to transform product visions for industry-leading GPU computing networks.
In order to solve the critical bottleneck in next-generation computing workloads, this company is seeking highly motivated and talented engineers who are excited to grow in a fast-paced startup environment.
This role might be ideal for you if you have:
- Experience designing and verifying large-scale networking and computing semiconductor chips
- Successful track record verifying chip- and block-level RTL designs
- Deep knowledge of SystemVerilog, UVM constructs, components, and practices, as well as Python/other scripting languages
- Hands-on experience with products that have shipped in high-volume
- BSEE/CE or MSEE/CE + professional experience in a relevant industry
Hybrid in the Bay Area, CA or Raleigh, NC.
Mia Macdonald
Semiconductor & Chip Design Recruiter