Senior Physical Design Engineer
GW122
Posted: 04/11/2025
- $200,000-$250,000
- United States
- Permanent
About the job
Acceler8 Talent is partnered with a well-funded semiconductor startup pioneering next-generation in-memory compute architectures (with a twist) is seeking a Senior Physical Design Engineer to join its world-class silicon implementation team. The company is redefining performance-per-watt for AI and data-intensive workloads through novel compute-in-memory technology and tightly integrated digital design, enabling scalable, energy-efficient computing for the next era of artificial intelligence.
In this role, you’ll drive the physical implementation of advanced AI accelerators, from floorplanning and synthesis through place-and-route, timing closure, and tape-out. You’ll work closely with architecture, circuit design, and verification teams to deliver high-performance, low-power silicon optimized for in-memory compute.
Responsibilities
Own full-chip and block-level physical design implementation (floorplanning, synthesis, P&R, STA, DRC/LVS sign-off).
Collaborate with architecture and RTL teams to ensure physical feasibility, power, and performance alignment.
Drive timing closure and optimize designs for power, performance, and area (PPA).
Develop and maintain physical design methodologies, scripts, and automation flows (TCL, Python, Make).
Interface with foundry and EDA vendors to debug tool or flow issues and improve design efficiency.
Support silicon bring-up and post-silicon correlation activities as needed.
Qualifications
BSEE/BSCE or equivalent experience.
10+ years of experience in physical design for complex SoCs or AI accelerators.
Deep expertise in synthesis, floorplanning, clock tree design, place-and-route, and STA using industry-standard tools (Synopsys, Cadence, or equivalent).
Strong scripting skills (TCL, Python, or Perl) for flow automation and optimization.
Proven ability to work cross-functionally with design, verification, and architecture teams.
Experience with low-power design techniques, hierarchical implementation, and advanced process nodes (5nm–16nm).
Tape-out experience with successful silicon in production is a strong plus.
Luke Tomaszko
Senior Semiconductor & Chip Design Recruiter